Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation are outstripping the benefits of voltage reduction and feature size scaling. Designers thus are continuosly challenged to come up with innovative ways to reduce power, while trying to meet all the other constraints imposed on the design.

In this talk we will discuss the issues that make it hard to reduce power in high-end CPUs. We will also discuss why CAD tools haven't been very helpful in this domain. We will then look at the techniques that have worked in real designs and point out relevant directions that need to be researched further.

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