Hiroshi Murata

Hiroshi Murata received his B.E. degree in EE from Kanazawa Univ., Japan, in 1980, and his master degree and Ph.D in CS from JAIST, Japan, in 1994 and in 1997, respectively.

His industrial experience is mainly from Hybrid IC and PCB design for analog circuits, through the in-house CAD group leader responsibility for about 13 years in Murata Mfg., Co. Ltd, Japan.

His research interest is in the physical design algorithms, especially in soft block optimization and timing optimization algorithms for building block type LSIs.

He will be staying at Berkeley, at Prof. Kuh's group, until March 1998.

Contact phone: 510-642-4332
Email address: murata@ic.eecs.berkeley.edu