CAD for Electrothermal Reliability of Deep Submicron VLSI


As the chip size and the integration level of system-on-chip (SOC) increase along with the clock frequency, the reliability issues due to high temperature rise, so-called electrothermal reliability issues, become critically important. VLSI designers need to be able to predict and fix such potential failures before fabrication. Unfortunately, existing CAD tools do not provide adequate design support. Hitherto simulation methods have emphasized only electrical behaviours such as timing for uniform temperature neglecting significant on-chip temperature variations. Also, no global models for MOS transistors including breakdown region have been used in SPICE-like circuit simulation. In this talk we discuss new CAD methods and tools developed at the University of Illinois over the last several years. Particular reliability concerns addressed in this talk are thermal failures of I/O frame due to electrostatic discharge (ESD) damages, electromigration (EM) failures of on-chip interconnects due to high current density and high temperature rise, and delay faults due to high local temperature variations on chip.

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