Static Noise Analysis for Advanced Digital VLSI Design and Cutting-Edge Silicon Technologies
Noise immunity has become a metric of comparable importance to area, timing, and power for the analysis and design of digital VLSI circuits. In this talk, I will describe the current status of static noise analysis techniques which have been developed over the last two years and are being commercialized today for leading-edge designs. I will describe the challenge of handling aggressive circuit styles, such as domino, pass-gate, DCVS, and self-resetting, and advanced technologies, such as low-threshold-voltage FETs, SOI, and copper interconnect. Despite these challenges, both technology and aggressive circuit design are pushing all electrical analysis tools (timing, power, noise) to combine transistor-level analysis with advanced interconnect modelling.