HW/SW Co-verification with Synopsys EagleI


Abstract

There have been few successful attempts to run application software packages on simulated hardware (VHDL or Verilog). Most of the problem has been attributed to a lack of processor performance in hardware simulation, but there is more to making this marriage work than processor cycles. Hardware and software development teams are separated by different tools, specification interpretations and development methodologies. Among the differences in tools are dissimilar human interfaces, which discourages a unified environment for Virtual System Integration or a virtual prototyping effort. This talk is about a new approach towards support of rapid system virtual prototyping, melting current hardware and software development environments, called Virtual System Integration. It provides for the rapid execution of target software applications as they are simulated in a virtual system modeled in VHDL or Verilog. This approach also supports the respective development tools and debugging environments available today to hardware and software engineers. Our goal is to provide a unified design verification environment that can be used earlier in the design process than is typical today, enabling designers to find integration level defects before a costly hardware prototype is built.


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