Logical Effort: Designing for Speed on the Back of an Envelope


Abstract

Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort, originally developed by Ivan Sutherland and Bob Sproull, formalizes the insights of experienced designers to make high-speed design easier and more methodical, providing a simple and broadly applicable method to choose circuit topologies and gate sizes for least delay. Come prepared to participate and learn techniques to help your own design.


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