Design Closure for Very Deep Submicron ASICs
Physical design is the process of creating a production worthy GDSII (a format describing the complete layout that can be fabricated), from a gate-level netlist and a set of constraints. In this talk I will discuss the challenges of a physical design flow for multi-million gate deep submicron designs. I will discuss two key issues. First, the interdependencies of various logical and physical variables and why they must be considered simultaneously during the physical design process. Second, the flow itself and its convergence - what needs to be done, how, and when? I will discuss several critical problems that an effective flow must address and outline some possible solutions.
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