Synthesis of asynchronous circuits with relative timing assumptions
We will first discuss why asynchronous is of interest.
Then we presents a design flow for high-performance asynchronous control circuits. It is based on lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system.
Lazy transition systems can be effectively used to model the behavior of asynchronous circuits in which relative timing assumptions can be made on the occurrence of events. These assumptions can be derived from the information known a priori about the delay of the environment and the timing characteristics of the gates that will implement the circuit. The method presents necessary conditions to generate circuits and a synthesis algorithm that exploits the timing assumptions for optimization. It also includes a technique for back-annotation that derives a set of sufficient timing constraints that guarantee the correctness of the circuit.
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