Extraction and measurement of high-speed on-chip interconnect

K. Shepard

Abstract

We will describe recent work to develop the first commercial full-chip, three-dimensional, shares-based, RLCK extraction tool. The technique of return-limited inductances is used to provide a sparse, frequency-independent inductance and resistance network with self-inductances that represent sensible ``nominal" values in the absence of mutual coupling. Mutual inductances are extracted for accurate noise analysis. The tool, Assura RLCX, exploits high-capacity scan-band techniques and disk caching for inductance extraction as an extension to Cadence's existing Assura RCX extractor. Interconnect response is part of a bigger picture in which high-speed digital design is becoming increasingly analog. We will also describe recent work on examining the feasibility of integrating primitive sampling oscilloscopes on-chip to provide waveforms of selective critical nets for test and diagnosis. The oscilloscopes rely on subsampling techniques to achieve sub-10 psec timing accuracy. High speed samplers are combined with DLLs and a simple 8-bit ADC to convert waveforms into digital data that can incorporated as part of the chip scan chain. We will describe the design and measurement of a chip we have fabricated to to incorporate our oscilloscopes with a high-frequency interconnect structure in a TSMC 0.25 um process.


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