Electronic Systems Design Seminar
http://embedded.eecs.berkeley.edu/esd-seminar


Design Technology and Architectural Adaptation for Embedded Systems-on-Chip

Prof. Rajesh Gupta
University of California, Irvine

Friday, May 3, 2002, 11:00am-12:00pm
540AB Cory Hall (DOP Center Classroom)

 

Abstract

Continuing trends in microelectronic technology and its integration are beginning to fundamentally alter the ground rules in the design of high performance system blocks, their interconnections and the role of software in system design. We are particularly interested in understanding the impact of these technology trends for the on-chip system architecture and design tools for the coming generations of process technologies. In particular, at the micro-architectural level increased local decision making can be used to adapt a data-path to application-specific computational requirements. This talk presents the case for a new class of system architectures -- for a range of embedded applications -- that use architectural customization to achieve system goals while keeping system development and product costs down. I will describe highlights from the on-going research activity on the AMRM and COPPER projects that use architectural adaptation and compiler control to improve the performance of the memory subsystem and communication resources.

This talk describes on-going research activity. We welcome participation and feedback from the audience. Further details on related projects and publication pointers can be found at http://www.ics.uci.edu/~rgupta.

Speaker

Rajesh Gupta (Ph. D. Stanford, M.S. UC Berkeley) is a professor of Information and Computer Science at UC Irvine. His research interests are in system-level design for embedded and portable systems. He has authored or co-authored over 100 articles on various aspects of microelectronic design/CAD. He is co-author of three issued patents on PLL design, system-level design modeling and on data-path synthesis. At UCI, he leads an effort on Adaptive Memory System Architectures and co-leads an effort on Compiler-Controlled Power/Performance Management; both sponsored by DARPA programs. Gupta is a recipient of the UCI Chancellor's Award for excellence in undergraduate research, a National Science Foundation Career Award, two Departmental Achievement Awards and a Components Research Team Award at Intel. Gupta serves as editor-in-chief of IEEE Design and Test and on the editorial boards of IEEE Transactions on CAD and IEEE Transactions on Mobile Computing. He is a Distinguished Lecturer for the ACM/SIGDA and the IEEE Circuits and Systems Society for 2000-2001.

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