Electronic Systems Design Seminar
http://www-cad.eecs.berkeley.edu/esd-seminar


FORTE -- 
INTEL's FORmal Tools Environment

John Moondanos
Visiting Industrial Fellow
Intel Inc., Santa Clara, CA

 

Monday, January 27, 2003, 4:00pm-5:00pm
540AB Cory Hall (DOP Center Classroom)

 

 

Abstract

INTEL's FORTE is an integrated and yet extendible environment for the development of Formal Verification tools.
It comprises of:

        FL: An interpreter for a general, strongly typed, functional language.

        METHLIB: A library of FL functions providing strong capabilities for common tasks.

        BDD: An efficient package providing the Intel implementation of Reduced Ordered BDDs with state of the art versions of all the known algorithms in the area.

        STE: Symbolic Trajectory Evaluation, a symbolic simulator with delay modeling capabilities.

        FSM: A data model for the representation of logic circuits.

        CKTVIEW: A graphical Visualization Environment for circuits.

Recently INTEL made available FORTE through its Open Source Website for academic research.

Speaker

Dr. John Moondanos received his BSEE with honors from the National Technical University of Athens, Greece in 1988, and his MSE and Ph.D. degrees from the Electrical and Computer Engineering Department of the University of Texas at Austin in 1990 and 1993, respectively. Subsequently he joined INTEL Corp. where he continues to pursue his research interests in the areas of microprocessor design, verification and test. From 1995 to 1998 Dr. Moondanos was responsible for the formal verification activities of the Pentium Pro and Pentium III microprocessors. From 1998 to 2001 he worked on the development of key components of INTEL's formal equivalence verification system. Since 2001 he is a Visiting Industrial Fellow from Intel Corp. at the Electrical Engineering and Computer Science Department of the University of California at Berkeley working on the Metropolis System.

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