Electronic Systems Design Seminar


Leakage Modeling and Reduction

Lei He
University of California at Los Angeles

Monday, April 12th, 2004, 4pm - 5pm
540A/B Cory Hall (D.O.P. Center Classroom)


The high leakage devices in nanometer technologies as well as the low activity rates in system-on-a-chip (SOC) contribute to the growing significance of leakage power at the system level. We first present system-level leakage-power modeling and characteristics and discuss ways to reduce leakage for caches. Considering the interdependence between leakage power and temperature, we then discuss thermal runaway and dynamic power and thermal management (DPTM) to reduce power and prevent thermal violations. We show that a thermal-independent leakage model may hide actual failures of DPTM. Finally, we present voltage scaling considering DPTM for different packaging options. We show that the optimal V_dd for the best throughput may be smaller than the largest V_dd allowed by the given packaging platform, and that advanced cooling techniques can improve throughput significantly.


Dr. Lei He obtained Ph.D. degree in computer science from UCLA, and is currently an assistant professor at electrical engineering, UCLA. From 1999-2001, he was a faculty member at electrical and computer engineering, University of Wisconsin, Madison. He also held industrial positions with Cadence, HP research, Intel, and Synopsys. His research interests include computer-aided design of VLSI circuits and systems, interconnect modeling and design, programmable logic and interconnect, and power-efficient circuits and systems. Related publications are available at http://eda.ee.ucla.edu.

He was granted the NSF early faculty career development award in 2000, the UCLA Chancellor's faculty career development award in 2003, and IBM faculty partner award in 2003.

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