Electronic Systems Design Seminar
http://www-cad.eecs.berkeley.edu/esd-seminar


 

Coordination Strategies for Correct-by-Construction
Design of SOCs and Embedded Systems

Luca Carloni

EECS Dept., University of California at Berkeley

Tuesday, May 11th, 2004, 4pm-5pm
540A/B Cory Hall (D.O.P. Center Classroom)
Dissertation talk & joint ESD/CHESS seminar

Abstract

Heterogeneity and distribution are becoming key properties of both high-performance integrated circuits and real-time embedded systems. For instance, the embedded electronics of a modern car includes a heterogeneous mix of components (ECUs, sensors, actuators...) and networks (CAN, FlexRay, MOST...) that constitutes a distributed architecture. In several application areas, this kind of architecture is the target for the deployment of safety-critical embedded software, which may account for up to 70% of the system's development cost. Similarly, systems-on-chip (SOCs) are increasingly hosting components of various nature (custom hardware, programmable units, analog/RF...). In this case, the combined impact of interconnect scaling, power dissipation, and process variations forces designers to consider the chip as a distributed system.

The key to addressing these challenges is the development of methodologies based on formal methods that enable modularity, flexibility, and reusability in system design. By working at the system level, I illustrate how these methodologies can take advantage of the commonalities that exist between IC design and embedded software programming. Specifically, focusing on timing issues in distributed system design, I explain the benefits of combining the theoretical properties of synchronous specifications with the efficiency of heterogeneous implementations where the constraints imposed by synchrony are relaxed. This idea is at the basis of our work on the deployment of embedded software on distributed heterogeneous architectures as well as the theory of latency-insensitive design. In particular, I describe the latter as the foundation of a correct-by-construction methodology that handles the increasing impact of interconnect latency on nanometer technologies and that facilitates the reuse of intellectual-property cores for building complex SOCs.

Speaker

Luca Carloni is a Ph.D. candidate in the EECS Department of the University of California at Berkeley advised by Professor Alberto Sangiovanni-Vincentelli.  Luca received his M.S. in Electrical Engineering and Computer Sciences from the the University of California at Berkeley and his Laurea degree (B.S.) from the Department of Electronics, Computer Science, and Systems of the University of Bologna, Italy. His research interests include design technologies for electronic systems, digital integrated circuits, embedded systems design, and computer architecture.


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