Electronic Systems Design Seminar

 JoAnn Paul

High-Level Performance-Power Simulation of Heterogeneous Multiprocessors Through Resolution of Design Layers

JoAnn M. Paul
Carnegie Mellon University

Monday, March 8th, 2004, 4pm - 5pm
540A/B Cory Hall (D.O.P. Center Classroom)


With the possibility of a hundred ARM equivalent processors to be placed on single chips within the next five years, individual processing elements can become like registers were in the early days of VLSI design -- fundamental building blocks. However, unlike registers they will be individually programmable. And yet, layers of programming begin to emerge in the resulting Programmable Heterogeneous Multiprocessors, where not only will individual processing elements be programmable, but inter-processor groupings as well as the chip as a whole must be considered programmable. A key design problem for these systems is how and when to group design elements. This must be captured by modeling and simulation but at a reduced level of detail, so that a broad design space may be explored. We introduce a new power-performance designstrategy, spatial voltage scaling, enabled by a new high-level simulator, MESH. Applied to a system that processes documents with mixed text and image elements, the exploration of a design space using spatial voltage scaling achieves both a 15% latency improvement and 66% power improvement over the baseline design even when all designs use a dynamic shutdown scheduling policy. The exploration of even this 8-10 processor design space required MESH in order to converge on the optimal design.


Dr. JoAnn M. Paul is currently Research Faculty in the Electrical and Computer Engineering Department at Carnegie Mellon University since 2000 where she has been working in the MESH group to define new chip level design abstractions and the design tools to support them.

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