Electronic Systems Design Seminar
http://www-cad.eecs.berkeley.edu/esd-seminar


 Greg Stitt

Warp Processors: Improving Software
Performance with Configurable Logic

Greg Stitt
UC Riverside

Monday, March 1st, 2004, 4pm - 5pm
540A/B Cory Hall (D.O.P. Center Classroom)

Abstract

Processors that dynamically optimize their software can improve speed and energy by performing aggressive optimization on critical kernels and by tuning those kernels to frequent data values seen at runtime. Additionally, partitioning critical kernels onto a field-programmable gate array (FPGA) coprocessor is known to achieve speedups and energy savings an order of magnitude better than any software optimizations in many cases. Until now, though, dynamic hardware/software partitioning was never considered feasible. Previous work on binary-level hardware/software partitioning, decompilation, and lean hardware synthesis algorithms, shows that dynamic partitioning is indeed feasible. In this talk, we present a new type of processor, which we call a warp processor. A warp processor executes a standard software binary on a traditional microprocessor, detects critical kernels, and then automatically and transparently moves those kernels to an FPGA coprocessor, essentially warping the execution time of each kernel by an order of magnitude or more. We describe the architecture’s main features, discuss design tradeoffs we considered, and provide initial speedup and energy results for embedded system benchmarks.

Speaker

Greg Stitt is a PhD student in the Department of Computer Science and Engineering at the University of California, Riverside. His research interests include hardware/software partitioning and low-power embedded system design. Stitt has a BS in computer science from the University of California, Riverside. He is a member of the IEEE.



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