EECS 298-11: CAD Seminar
Wednesday, February 1, 5pm
531 Cory Hall, Hogan Room

	Hierarchical Models of Synchronous Circuits

		Prof. David L. Dill
		Stanford University

We seek a behavioral model of synchronous circuit operation
which generalizes Mealy machines in several ways:

*  It should allow the expression of nondeterministic behavior.

*  It should allow parallel composition of machines and hiding
   of output signals.

*  It should not restrict bidirectional communication between
   machines.

*  It should deal reasonably with zero-delay cycles, which can be
   present in unrestricted communication graphs.

*  It should provide a preorder that precisely captures the proper
   relationship between implementation and specification behaviors.

*  It should allow the computation of the "most general environment"
   of a circuit.

Suprisingly, given the attention that has been paid to switching
theory over the years, no adequate model exists meeting these
criteria.  Devising such a model is more challenging than we had
expected.  This talk is a description of several of the specific
problems that arise, along with solutions to some of them.

This is joint work with Jerry Burch and Elizabeth Wolf.


Future Seminars:

February  8 - Masahiro Fujita, Fujitsu Labs
              "Logic Verification and Synthesis with Temporal Logic"

February 15 - Medhi Hatamian, SDE
              "A Design Environment for Multi-Million Transistor
               Chip Design: Created by Designers for Designers"
 
February 22 - Forrest Brewer, UC Santa Barbara