EECS 298-11: CAD Seminar
Wednesday, May 10, 5pm
531 Cory Hall, Hogan Room

        Code Generation and Optimization for Embedded DSP Processors
       
                              Stan Y. Liao
                                  MIT

Microprocessors such as microcontrollers and fixed-point digital signal
processors (DSPs) are increasingly being embedded into many electronic
products.  Two trends are becoming clear in the design of embedded systems.
First, cost, power and reliability considerations are forcing designers into
taking the next step: incorporating all the electronics---microprocessor,
program ROM and RAM, and application-specific circuit components---into a
single integrated circuit.  Second, the amount of software incorporated into
embedded systems is growing larger and more complex.  The first trend elevates
code density to a new level of importance because program code resides in
on-chip ROM, the size of which translates directly into silicon area and cost.
The second trend mandates the use of high-level languages (HLLs) in order to
decrease development costs and time-to-market.

While optimizing compilers have proved effective for general purpose
processors, the irregular datapaths and small number of registers found in
embedded processors, especially fixed-point DSPs, remain a challenge to
compilers.  The direct application of conventional code optimization methods
has, so far, been unable to generate code that efficiently uses the features of
fixed-point DSP microprocessors.  We believe that generating the best code for
embedded processors will require not only traditional optimization techniques,
but also new techniques that take advantage of special architectural features
and that decrease code size.  In this talk we will address several problems
that arise in code generation for embedded DSP processors and present solutions
to these problems. In addition to the tasks of instruction selection,
scheduling, and register allocation, we will examine the problems of storage
assignment and code compression.

Future Seminars:

May 17: Carl Sechen, Universty of Washington
        "Symbolic Analysis for Large Analog ICs"

End of semester