EECS 298-11: CAD Seminar
Wednesday, May 8, 1996, 5pm
531 Cory Hall, Hogan Room


      The Avalanche Scalable Parallel Processor:
        An Overview of its Design and Formal Validation

		Ganesh Gopalakrishnan
		Univ. of Utah
 
The Avalanche scalable parallel processor project at the
Department of Computer Science, University of Utah (sponsored
by SPAWAR and ARPA, and in collaboration with Hewlett-Packard)
seeks to develop a scalable high-performance parallel processor
based on HP-PA processors and the Myricom communication fabric.
As with several other well known projects, Avalanche
provides both distributed shared memory (DSM) and message passing (MP)
capabilities.

Formal verification methods are being applied at numerous levels
of the Avalanche processor design. This effort has exposed some of
the challenges of applying formal verification methods to state-of-the-art
designs, revealed the potential to detect actual design errors, and also
given us some insights into how to tackle the verification complexity.
 
This talk will be on the design of Avalanche and our formal verification
techniques.
For more information, please see http://www.cs.utah.edu/projects/avalanche


Upcoming seminars:

May 10 (Friday 11am):  Dhiraj Pradhan, Texas A & M Univ.