EECS 298-11: CAD Seminar
Wednesday, February 14, 1995, 5pm
400 Cory Hall, Hughes Room


Multi-FPGA Systems

Scott Hauck
Northwestern University
Department of Electrical Engineering & Computer Science
Evanston, IL

Field-Programmable Gate Arrays (FPGAs) are chips that can be electrically
programmed and reprogrammed to implement complex, multi-level logic.  While
commonly thought of as an implementation medium for glue-logic on circuit
boards, they offer great potential for many roles.  As a logic emulation
system, they offer orders of magnitude speedup for the simulation and
verification of integrated circuits.  As a custom-computing device, they
provide world-class performance for numerous applications, including
genetic string-matching and data encryption.

One of the keys to efficiently harnessing the power of FPGAs is the
automatic software that maps circuits and algorithms to multi-FPGA systems.
In this talk I discuss such software, including logic partitioning and pin
assignment algorithms, as well as some architectural considerations.  Logic
partitioning is the process of breaking mappings into FPGA-sized pieces,
and I present bipartitioning results significantly better than the
state-of-the-art.  I also present a pin assignment algorithm, an algorithm
for routing signals between FPGAs, that greatly decreases the time
necessary to map a circuit to a multi-FPGA system, while also improving the
routing quality.  Finally, I detail how multi-FPGA systems should be built,
and present routing topologies that decrease routing resource requirements
while increasing bandwidth.  I conclude with some future directions,
including rapid-prototyping systems for board-level designs, as well as
ideas for augmenting general-purpose processors with reprogrammable logic.

Next Seminar:
Feb 21: Alex Saldanha, Cadence Berkeley Labs