EECS 298-11: CAD Seminar Wednesday, February 21, 1995, 5pm 531 Cory Hall, Hogan Room Compact Complete Test Sets for Multiple Stuck-Faults ==================================================== Alexander Saldanha Cadence Berkeley Laboratories Test set generation for all detectable multiple stuck-faults in a circuit is widely recognized as being important for obtaining high defect coverage in manufactured circuits. This talk describes a procedure that generates a complete test set for multiple stuck-faults in any combinational logic circuit. The approach is novel in that it does not perform explicit test pattern generation, fault simulation, or fault enumeration of the multiple stuck-faults. The algorithm attempts to find a set of vectors, typically with only two vectors, that detects every detectable multiple stuck-fault that contains a target single stuck-fault. Experimental results on small to moderate size benchmark circuits yield complete test sets that are on average twice as large as a test set that only detects all single stuck-faults. Joint work with Alok Agrawal, Luciano Lavagno and Alberto L. Sangiovanni-Vincentelli. Upcoming Seminars: 2/26/96 (Monday 2pm Wang room): Egon Boerger, Universita di Pisa A formal specification and a correctness proof for pipelining in RISC architectures 2/28/96: Ramin Hojati, UC Berkeley Datapath Abstraction in Hardware Systems 3/6/96: Steve McGeady, Intel Internet Technology Lab 3/13/96: Yogen Dalal, Mayfield Fund 3/20/96: Thomas A. Henzinger, UC Berkeley