EECS 298-11: CAD Seminar
Wednesday, January 29, 1997, 5pm
Cory Hall--Hogan Room

                         Synchronous Verilog

                           Ching-Tsun Chou
                   Fujitsu Laboratories of America


Recent research on synchronous languages, in particular Esterel, has
shown that they are ideal for describing the functional aspect of
synchronous hardware, because (a) their semantics, based on the
synchrony hypothesis, is at the right level of abstraction; (b) they
offer powerful constructs for expressing various notions of control
flow; and (c) they support natural translation into synchronous
circuits which can be optimized to produce efficient hardware in many
cases.  Unfortunately, the two dominant hardware description languages
of today, Verilog and VHDL, are based on discrete-event simulation,
which is at too low a level of abstraction for describing the
functional aspect of synchronous hardware.  But Verilog does have a
rather rich set of control constructs, including those for
concurrency, sequencing, and preemption that can be freely nested.  Is
it possible to do Esterel-like synchronous programming in Verilog?

In this talk I would like to give an affirmative answer to this
(admittedly vague) question.  Specifically, I will attempt to show
that it is possible to:

(1) identify a subset of Verilog, called SV (Synchronous Verilog), to
    which we can give an Esterel-like reading in a consistent manner;

(2) define a translation from SV programs to synchronous circuits that
    serves as the synchronous semantics of SV;

(3) maintain the following connection between the synchronous
    semantics and the simulation semantics of SV: for every SV
    program, every execution of the synchronous semantics is (the
    abstraction of) an execution allowed by the simulation semantics,
    which furthermore can be "forced" by inserting zero-delays into
    the SV code.

This talk may be of interest to people working in cycle-based
simulation, synthesis, and system description languages.