EECS 298-11: CAD Seminar
Wednesday, January 22, 1997
Cory Hall--Hogan Room

       Research Activities at the IBM Austin Research Laboratory

             David LaPotin, Anirudh Devgan, Sani Nassif
		IBM Austin Research Laboratory

	10:30am - 11am	David LaPotin  (Introduction)
	11am    - 12am	Anirudh Devgan (Transistor-level timing simulation)
	5pm     - 6pm	Sani Nassif    (Design for Manufacturing)

The seminar will begin with a description of the various research activities 
at the IBM Austin Research Laboratory, with a specific focus on high
speed microprocessors. Next, two key CAD research activities in the
areas of transistor level-timing simulation and design for manufacturing
will be described in detail.

Timing verification is a critical and time consuming step in design of
integrated circuits. Design of state-of-the-art high performance
circuits require increasingly greater emphasis on transistor level
timing verification.  This talk will present recent transistor level
timing verification techniques, covering dynamic timing simulation,
interconnect analysis and static timing analysis.

Design and manufacturing uncertainties reduce our ability to
design and tune circuits for maximum performances, and leads to
a delicate balance between yield (manufacturability) and profit (related
to performance). This talk will explore the current state of the
art in design-oriented manufacturability analysis and optimization,
and illustrates the prevailing industrial techniques with examples.