EECS 298-11: CAD Seminar Wednesday, April 23, 1997, 5pm Cory Hall--Hogan Room Design Flow: Understanding the issues beyond basic synthesis, placement and routing Lou Scheffer Cadence Design Systems Designers building industrial chips must meet many requirements other than those imposed by the basic synthesis, placement, and routing algorithms. Many of these practical requirements are easy to incorporate into new CAD tools, but are difficult to retrofit later; others provide potential topics for new research. In any case, understanding how designers use CAD in the field is a good first step towards the development of new and better tools. This talk goes through the flow, developed by a major industrial manufacturer, intended to guide users through all the required steps. This flow reveals a number of issues that must be solved in practice, but are not commonly the subject of research. These include: picking a package, and its effect on CAD tools; libraries and tools that work with both VHDL and Verilog; timing constraints both for the end application and the tester; JTAG and other test methods, and their impact on CAD tools; practical constraints on the placement of embedded blocks; placing the IOs (needed to start quadratic placement); estimating clock delay and skew before the clock is designed, for both clock trees and clock trucks; making logic changes after placement based synthesis has changed the netlist; back annotation to original Verilog/VHDL, after synthesis/clock trees/manual changes have changed the netlist; and so on.