The Sensitivities of New High Speed CMOS Circuit Styles


Abstract

The quest for CMOS microprocessor performance has led to increased use of "alternative" circuit families. These families, which include pass-transistor and domino structures, reduce delay by (1) removing PFETs from the delay path; (2) increasing the logic content of each delay stage; (3) decreasing input capacitance; and (4) optimizing technology usage. In addition, these families support innovative approaches to resolving clock skew and noise problems.

These alternative styles also present new process sensitivities and fail mechanisms which significantly differ from those associated with common static CMOS, and which must be modeled in the chip design. This presentation first reviews these newer styles, and then explores their process and application preferences. Insights drawn from actual IBM product experience will be shared.


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