Reliability Estimation of VLSI Circuit Design

Abstract

The dramatic and continuing decrease in feature size into deep submicron regime and the corresponding increase in the number of devices on a chip have made reliability another critical design objective that needs to be included in the design of VLSI circuits and systems. This talk will present an overview of ongoing work on reliability estimation of deep submicron VLSI circuits. The reliability issues we address include power, voltage drop, ground bounce, electromigration, heating, and noise. We focus on estimating worst-case conditions and study the interaction between the logic design and the interconnects, including the power bus.

Exisitng tools on reliability estimation that are available from CAD vendors can be classified as "back-end" tools. They rely on "direct simulation" in which the design is simulated at the transistor-level with a set of user-specified input signals to obtain current waveforms drawn by each subcircuit in the design. The current waveforms are then used to compute maximum and average power. They are also applied at contact points to the power and ground bus models to compute voltage and current waveforms in the bus. These waveforms are then processed to find voltage-drop and electromigration estimation. Such an approach is accurate for the input signal set specified, but is computationally expensive and does not guarantee worst-case conditions. In addition, such an approach does not give easy indications as to which parts of the design cause reliability problems, if such problems are detected.

Our approach, in contrast, is input-independent and fast, and can be applied as part of the design process. The approach relies on static timing analysis and logic implication to generate tight upper bounds on worst-case conditions. It also indicates which parts of the design may cause reliability problems for possible design modifications. Applications will be included.