Farid Najm

Farid N. Najm received the B.E. degree (with distinction) in electrical engineering from the American University of Beirut (AUB) in 1983, and the M.S. and Ph.D. degrees in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1986 and 1989, respectively.

He worked with the General Swedish Electric Company (ASEA) in Vasteras, Sweden, in 1982, and was a teaching assistant at AUB in 1983. He later worked as Electronics Engineer with AUB from 1983 to 1984 and held a visiting position with the University of Warwick, England, in 1984. While at the University of Illinois, 1985-1989, he was a research assistant with the Coordinated Science Laboratory, and worked for a year with the VLSI Design Lab. at Texas Instruments Inc. in Dallas, Texas. In July 1989, he joined Texas Instruments as Member of Technical Staff with the Semiconductor Process and Design Center. In August 1992, he became an Assistant Professor with the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign, and was promoted to Associate Professor in 1997. Dr. Najm received the IEEE Transactions on CAD Best Paper Award in 1992, the NSF Research Initiation Award in 1993, and the NSF CAREER Award in 1996. He is Technical Program Co-Chairman for the International Symposium on Low-Power Electronics and Design (ISLPED), 1998, and was technical program chairman for the 1997 Great Lakes Symposium on VLSI. He has served on the technical committees of ICCAD, DAC, CICC, and ISLPED and is a Senior Member of the IEEE. He is Associate Editor for the IEEE Transactions on VLSI, and has served as column editor for the IEEE Circuits and Devices Magazine, 1996-97. He has also served as guest editor for the VLSI Design journal, and for the High Speed Electronics and Systems journal, both in 1994. His research interests are in the general area of CAD tool development for VLSI circuits, including power estimation, modeling, and optimization, low-power design, reliability prediction, synthesis of low-power and reliable VLSI, timing analysis and verification, test generation, and circuit and timing simulation.

Email address: najm@uiuc.edu