Spring 1998 CAD Seminar Schedule

  • Click on the speaker's name for a brief biography and contact information
  • Click on the title for a abstract of the talk. If we have electronic copies of transparencies or relevant papers,
    they can be found here, along with the abstract.
  • Please send comments and suggestions to the CAD seminar organizers.

    Month Date Day Time Venue Speaker Title
    January 21 Wed 5:00 pm Hogan Room P. Goel Doing an EDA Startup
    28 Wed 5:00 pm Hogan Room V. Singhal Symbolic Procedures for a Theory of Equality
    February 4 Wed 5:00 pm Hogan Room K. Bernstein The Sensitivities of New High Speed CMOS Circuit Styles
    10 Tue 1:30 pm 373 Soda L. Benini Low power design: challenges and perspectives
    18 Wed 9:00 am Hughes Room A. Kuehlmann Verity: A Boolean Equivalence Tool
    18 Wed 5:00 pm Hogan Room E. Singerman Translation Validation
    25 Wed 5:00 pm Hogan Room N. Shankar Lazy Compositional Verification
    March 4 Wed 5:00 pm Hogan Room L. Pileggi Delay Metrics for the Next Fifty Years
    11 Wed - - - NO SEMINAR (ILP Conference)
    13 Fri 2:00 pm Hughes Room G. Janssen Implementing Logics for Hardware Verification
    18 Wed 5:00 pm Hogan Room J. Kukula Implicit Reachability Techniques for Presburger EFSMs
    20 Fri 1:00 pm 299 Cory J. Brzozowski Blanket Algebra for Decomposition of Functions
    25 Wed - - - NO SEMINAR (Spring Break)
    30 Mon 5:00 pm Hughes Room M. Fourman Formal Methods for System Integration
    April 1 Wed 5:00 pm Hogan Room F. Rahim and R. Bawa Formal Verification Tools for VHDL Based Systems
    8 Wed 5:00 pm Hogan Room T. Kam Formal Verification of Arithmetic Circuits
    15 Wed 5:00 pm Hogan Room O. Coudert A New Paradigm for Dichotomy-based Constrained Encoding
    17 Fri 2:00 pm Wang Room S. Hauck Configuration Memory Management for
    Adaptive Computing Systems
    22 Wed 5:00 pm Hogan Room I. Hajj Reliability Estimation of VLSI Circuit Design
    23 Thu 2:00 pm Hogan Room F. Najm High-Level Power Estimation and Modeling
    May 4 Mon 5:00 pm Hughes Room R. Ranjan On Retiming and Resynthesis Transformations
    6 Wed 5:00 pm Hogan Room S. T. Cheng Compiling, Synthesis, and Simulation of V++
    13 Wed 5:00 pm Hogan Room I. Wegener On the use of Nondeterminism in BDD Models

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