Solutions to the interconnect design and analysis bottleneck
AbstractRapid device scaling and the subsequent increase in switching speeds have highlighted the limitations of on-chip metal interconnects to carry fast signals while insuring low loss and high integrity. Effects such as signal crosstalk, bounce, and delay have become dominant due to reduction in metal width, ptich and width to height aspect ratio. In order to manage these effects, new circuit engineering methods, computer-aided design and verification techniques, and process technology variations will have to overcome the inherent limitations of metal in dielectric. An overview of the "interconnect problem" is presented and a discussion of possible solution diretions is given. Inductance usage, Logic/timing orthogonality, transmission line design, metal planes, full wave modeling and model reduction, hierarchical interconnects, computational area limitation, asynchronous design, and other techniques will be discussed.
Click here for slides : postscript
E. Chiprout, "Interconnect and Substrate Modeling and Analysis: An Overview" IEEE Journal of Solid-State Circuits, pp. 1445-1452, Vol. 33, No. 9, Sept. 1998.
A. Deutch, D.C. Edelstein, G.A. Sai-Halasz, E. Chiprout "CMOS7S BEOL definition for GHz clock frequencies", IBM research report RC-20581, Oct. 1996.
E. Chiprout, "Hierarchical interconnect modeling", International electron devices meeting (IEDM), Washington DC, Dec. 1997.
E. Chiprout and T. Nguyen, "Survey of model reduction techniques for analysis of package and interconnect models of high-speed designs", 6th topical meeting on electrical performance of electronic packaging (EPEP), San Jose, CA, Oct. 1997.
E. Chiprout, "Interconnect and substrate modeling and analysis: an overview" , proc. Bipolar/BiCMOS circuits and technology meeting (BCTM), Minneapolis MN, Sept. 1997.
R. Achar, M. Nakhla and E. Chiprout "Block CFH -- a model reduction technique for multiport distributed interconnect networks", European Conference on circuit theory and design", Aug. 1997, Budapest Hungary.
J. Phillips, E. Chiprout and D. Ling "A full-wave electromagnetic modeling code with model-order reduction and multilevel matrix decomposition", Progress in Electromagetics Research Symposium (PIERS), July, 1997, Cambridge, MA
T. Nuyen and E. Chiprout, "Application of Rational Krylov subsapce methods in model reduction for circuit simulation", presented at SIAM 45th anniversary meeting, Stanford Univ, July, 1997.
D. P. LaPotin, U. Ghoshal, E. Chiprout, S. R. Nassif "Physical Design Challenges for Performance", Proc. 1997 Int'l Symposium on Physical Design, pp. 225-226.
E. Chiprout, "An Error Bound in Interconnect Simulation using PRIMA" proc. IEEE signal propogation on interconnects conference, Travemunde, Germany, May, 1998.
M. Nakhla, E. Chiprout, R. Achar, R. Khazaka, "Recent progress in the simulation of high-speed VLSI interconnects", proc. IEEE 4th topical meeting on Electrical Performance of Electronic Packaging, Oct, 1995.
A. Ruehli and E. Chiprout, "The importance of retardation in PEEC models for electrical interconnect and package (EIP) applications", proc. IEEE 4th topical meeting on Electrical Performance of Electronic Packaging, Oct, 1995.
J. Phillips, E. Chiprout, D. Ling "Efficient full-wave electromagnetic analysis via model order reduction of fast integral transforms", Design Automation Conference, Las Vagas, June, 1996.
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