Interconnect-Limited VLSI Architecture


Abstract

As semiconductor technology scales, wires are becoming the dominant factor in determining system performance and power dissipation. Just a few years back, a signal could traverse an entire chip in less than a single clock cycle. Today designers of microprocessors must allow three clocks to traverse a chip. By 2008, it is expected that chip traversal will require 16 clocks. Modern superscalar architectures that depend on global register files, global bypass structures, and global instruction issue logic are poorly matched to tomorrow's semiconductor technology. This technology demands architectures that exploit latency and minimize global communication.

This talk introduces the problem of interconnect-limited architectures and discusses three projects underway at Stanford to develop architectures well-suited to tomorrow's semiconductor technology. The talk will also give a system-designer's perspective on the computer-aided design tools needed to support such developments.


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