Considerations of completeness of expression in the characterization of asynchronous circuits


Abstract

We begin with the notion of single form completeness of expression. If a process behavior can be expressed, for instance, completely in terms of logical relationships then the expression will not contain temporal relationships. This can be achieved with a logic that is impractical to implement. As we migrate from the impractical logic to practical logics, completenesses of expression become compromised which must be compensated for by the expression of temporal relationships. I believe that this conceptual approach provides a deeper insight into why and where delay sensitivities arise in digital circuits and how they affect design and performance.


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