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Altera's APEX 20K architecture and research in synthesis/fitting for
FPGA/CPLDs
Abstract
The talk will outline Altera's recent innovations in high density
programmable logic devices and
the new challenges to synthesis, partitioning, and place-and-route
algorithms for the new
architectures.
Altera's new APEX 20K archietcture combines Look-Up table, ROM logic and
Product-Term logic on the
same device requiring new advances in technology mapping. Furthermore, the
routing architecture
requires new paritioning and timing driven place and route algorithms. The
talk will progress by
briefly describing the architecture advances from FLEX 10K, FLEX 6000 to
APEX 20K. I will
outline the CAD algorithms involved in those architectures and the new areas
that Altera is
exploring for the APEX 20K architecture. The APEX 20K devices offer density
ranges up to 30,000
LUT elements + FFs not counting the embedded RAM and PTERM modes. With
devices so large, synthesis and
place and route compilation times increase heavily. I will end by proposing
research topics of interest to
the Programmable Logic industry in the upcoming years.
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