HW/SW Co-Verification Involving Digital Signal Processors


Abstract

The standard approach to HW/SW co-verification of embedded systems relies on instruction-accurate processor simulators wrapped with bus functional models (BFM) recovering the correct timing information of the pins from the high-level processor model. Contrary to their original role in HW testing, the BFMs used in HW/SW co-verification have to relate a generally infinite set of sequential events of the software to the infinite set of concurrent events taking place in the hardware. For processor architectures generating orthogonal software events the BFM transactions are independent and the correct pin timing can be provided using a simple logic. Recent digital signal processors (DSP) and an increasing number of new microcontrollers, however, have deep pipelines with memory accesses distributed over multiple pipeline stages and complex stall logic. In these cases the relation between software and hardware events becomes very complex and the standard BFM approach often fails. In the talk we present the cycle/phase-accurate approach to the modeling of pipelined processors. The processor is modeled in a full cycle/phase-accurate fashion with the complete simulation of the pipeline and all interrupt and stall effects. The advantage of this approach is the high simulation precision which reduces the BFM wrapper to its original function of describing the pins and their delays. In the talk the benefits and trade-offs of this approach with respect to simulation speed, verification methods and design time are discussed in the context of DSP-oriented system-on-chip development.


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