Spring 1999 CAD Seminar Schedule

  • Click on the speaker's name for a brief biography and contact information
  • Click on the title for a abstract of the talk. If we have electronic copies of transparencies or relevant papers, they can be found here, along with the abstract.
  • Please send comments and suggestions to the CAD seminar organizers.

    Month Date Day Time Venue Speaker Title
    January 20 Wed 5:00 pm Hogan Room Y. Gurevich Abstract state machines
    27 Wed 5:00 pm Hogan Room M. Khalaf Altera's APEX 20K architecture and research in synthesis/fitting for FPGA/CPLDs
    February 3 Wed 5:00 pm Hogan Room K.Fant Considerations of completeness of expression in the characterization of asynchronous circuits
    10 Wed 5:00 pm Hogan Room J. Meseguer Executable formal specification in Maude
    17 Wed 5:00 pm Hogan Room E. Chiprout Solutions to the interconnect design and analysis bottleneck
    24 Wed 5:00 pm Hogan Room N. Ip Generalized Reversible Rules
    25 Thurs 1:00 pm Hughes Room R. Tessier Frontier: A Fast FPGA Floorplanning and Routing System for Reconfigurable Computing
    March 3 Wed 5:00 pm Hogan Room V. Zivojnovic HW/SW Co-Verification Involving Digital Signal Processors
    10 Wed 5:00 pm Hogan Room P. Ho Formal Verification of Pipeline Control
    17 Wed 5:00 pm Hogan Room R. Panda CAD Challenges for High Performance and Low Power Processor Designs at Motorola.
    24 Wed 5:00 pm Hogan Room Spring Break No Seminar
    31 Wed 5:00 pm Hogan Room Y. Kukimoto Towards Robust False Path Analysis
    April 7 Wed 5:00 pm Hogan Room L. van Ginnekan Timing Closure Methodology
    14 Wed 5:00 pm Hogan Room B. Dally Interconnect-Limited VLSI Architecture
    20 Tue 3:30 pm Hughes Room M. Abromovici A Satisfiability Solver Using Reconfigurable Hardware and Virtual Logic
    21 Wed 5:00 pm Hogan Room P. Pan Retiming and its Applications
    28 Wed 5:00 pm Hughes Room S. Edwards Compiling Esterel into Sequential Code
    May 5 Wed 5:00 pm Hogan Room TBA TBA

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