SIS is an interactive program for the synthesis of both synchronous and asynchronous sequential circuits. The input can be given in state table format or as logical equations (for synchronous circuits), or as a signal transition graph (for asynchronous circuits); a target technology library is given in genlib format. The output is a netlist of gates in the target technology.

The system includes various capabilities that are controlled interactively by the user. These include state minimization, state assignment, optimization for area and delay using retiming, optimization using standard algebraic and Boolean combinational techniques from MISII, performance optimization using restructuring, and technology mapping for optimal area and delay. Redundancy removal and 100% testability are provided for combinational and sequential circuits. Formal verification is available for both combinational and sequential circuits, even for circuits with different state encodings.

The current release (1.2) contains SIS, NOVA (state assignment), JEDI (state assignment), STAMINA (state minimization, from June Rho at University of Colorado, Boulder), SRED (state minimization), ESPRESSO, BLIF2VST (BLIF to structural VHDL translator), VST2BLIF (structural VHDL to BLIF translator), XSIS (a front-end graphical interface to sis) and several stripped down packages from the OctTools (options, port, and utility) that are needed for some of the programs listed above. SIS-1.2 can be obtained via anonymous ftp from (

Last Updated 7/12/94.

You are not logged in 
©2002-2017 U.C. Regents