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Next: Flatten Up: VIS Previous: Describing Designs for VIS Verification In VISWhen a BLIF-MV description is read into VIS, it is stored as a ``hierarchy'' tree, which is a hierarchical description of the design; it consists of modules that in turn consist of sub-modules. The functionality of a module is represented by a network of gates with arbitrary functionality and latches. The print_hierarchy_stats command in VIS prints hierarchy information, and the print_models command lists statistics on all the models in the hierarchy. Other useful print commands are print_io and print_latches. The hierarchy in VIS can be traversed in a manner similar to traversing directories in UNIX, i.e., a desired node in the tree can be reached by walking up and down with the cd command. At any node, simulation, verification and synthesis operations can be performed. The command pwd prints the name of the current node. The command ls lists all the nodes (submodules) in the current node; ls -R lists all the nodes in the current subtree. We begin by describing the steps involved in converting this hierarchy description into an internal FSM representation. The compound init_verify command executes the entire sequence of required initialization commands.
Next: Flatten Up: VIS Previous: Describing Designs for VIS Roderick Bloem 2001-05-21 |