Directory+Main Memory +Arbiter

cache_Wlist[ ]

cache_Rlist[ ]

Directory+Main Memory +Arbiter

MAIN

MEM

CACHE

STATUS

REG

TWO

N Processor

Arbiter (2N states)

ONE

WAIT

TWO

WAIT

main_mem[ ]

ONE

blk_rreq1 && other (j) has

address in EXCLUSIVE

ok

ok

else

blk_rreq2 && other has

address in EXCLUSIVE

else

ok

ok

write_back_req(j)

TWO

SERVE

ONE

SERVE

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