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Fall 2011 Seminars
Patricia Derler, 16 Dec 2011
Last updated: 2 Feb 2012

Martin Toerngren, KTH, Sweden, Monday, September 19th, 2011

Timing problems and opportunities for embedded control systems; modeling and co-design

This presentation will address timing problems in the design of discrete-time feedback control systems and in their codesign with the embedded systems implementation. The talk will by way of introduction provide an embedded control systems demo to highlight central characteristics such as modes of operation, feed-forward, feedback, different timing constraints and urgence vs. importance. Perspectives to timing problems will be provided including a snapshot of engineering practices (mainly automotive), an overview of different types of timing requirements, deriving timing constraints for feedback controllers and codesign of controllers and their real-time implementation. The latter part of the talk will discuss gaps between control theory and scheduling theory, and address approaches for codesign encompassing different modeling abstractions.

Bio: Martin Toerngren studied Mechanical Engineering with a specialization in Mechatronics at KTH. After completing his Masters (Civ. Ing) in 1987 he began as a teacher at KTH, developing and giving courses in Mechatronics and Embedded systems. He was then offered a PhD student position which resulted in a dissertation in 1995: "Modeling and design of distributed real-time control applications". Since this area was then not very developed, the time as a PhD student included networking and creating PhD student courses. Examples of such activities included starting the interests groups on "Distributed control" and the "Swedish Transputers users group". In 1992 Martin Toerngren participated in the NATO Advanced Study Institute on Real-time computing. After his dissertation, Martin Toerngren co-founded the company Fengco Real-time Control AB, specializing in advanced tools for developers of embedded control systems and related consultancy. The following period, 1996-1999, was dedicated to building up a research group in the area of embedded control systems within the division of Mechatronics at KTH. During 1998, Martin Toerngren, spend 0,5 year as a post-doc at the European Commission Joint Research Centre in Ispra, Italy. He was appointed Professor at KTH for the new chair in Embedded Control Systems in 2002.

Alexandre Donze, Verimag, Grenoble, Monday, September 26th, 2011

Robust Satisfaction of Signal Temporal Logics and Applications

The Signal Temporal Logic (STL) is adapted to specify rigorously properties constraining real-valued, dense-time signals such as traces resulting from the simulation of continuous and hybrid systems. Recently, we extended STL with a quantitative (robust) interpretation which provides a numerical margin by which a simulation trace satisfies or violate a property. Moreover, we can estimate in some cases the sensitivity of this margin to a parameter change. By combining this information with different parameters exploration strategies, we get an efficient methodology to investigate which properties are satisfied by a model, how robustly these properties are satisfied and how to find parameters values which guarantees a robust satisfaction. I will describe this methodology and the toolbox which implements it, Breach, along with different application examples.

Bio: Alexandre Donze is a post-doctoral faculty at Verimag, Grenoble, working in the hybrid and timed system group lead by Oded Maler. This is also where and with whom, in co-supervision with Thao Dang, he did his thesis. From oct. 2007 to oct. 2008, he was a post-doctoral faculty at Carnegie Mellon University, working with Edmund M. Clarke and Bruce H. Krogh. In June 2009 he also started a collaboration with the TIMC laboratory (laboratory of techniques for biomedical engineering and complexity management), in particular with Eric Fanchon and Philippe Tracqui. The main goal of his research is to develop mathematical and computational tools for the analysis and the design of dynamical systems arising from different domains, in particular embedded systems (or software interacting with a physical environment), analog and mixed signal circuits and biological systems.

Christian Motika, Christian-Albrechts-Universitaet, Kiel, Germany, Monday, October 3rd, 2011

Synchronous statecharts for executing Esterel with Ptolemy

The statecharts formalism, proposed by David Harel, is a well known approach for modeling control-intensive tasks such like reactive systems. Synchronous languages like Esterel help to separate concerns w.r.t. the functionality and the timing of reactive systems. SyncCharts are the natural adaption of Harel statecharts to the synchronous world. Esterel programs can be transformed into their graphical SyncCharts counterpart. SyncCharts can be simulated using Ptolemy as a simulation backend. This talk covers an introduction into Esterel, SyncCharts, an overview of the transformation, and the simulation implemented in the KIELER framework.

Bio: Christian Motika is a Ph.D. student at the Christian-Albrechts-Universitaet zu Kiel, in northern Germany. He is part of the Real-Time and Embedded Systems Group of Prof. Reinhard von Hanxleden. Special interests are synchronous languages, model based design and concurrent programming. He finished his master thesis in late 2009 and is part of the collaboration between his group and the group of Prof. Edwards Lee at UC Berkeley.

Vigyan Singhal, Oski Technology, Monday, October 17th, 2011

Deploying Formal in a Simulation World

Missing bugs in hardware designs is expensive enough that the semiconductor industry routinely spends 2/3 of the design cycle in verifying the designs before tapeout. Formal verification technology has today advanced to the stage that it can complement or replace simulation effort for selected hardware designs. However, the adoption of formal in a chip design schedule requires (a) Planning, and deciding where to apply formal; (b) Verifying efficiently, often through the use of manually crafted abstractions; and (c) Measuring coverage at the end of the verification process, to determine how much was formally verified so fit the formal effort in the context of the popular simulation-based coverage metrics.

Bio: Vigyan Singhal is the CEO of Oski Technology, which specializes in applying formal verification on hardware designs. Vigyan was previously the founder and CEO of two VC-funded startups: Jasper Design Automation in EDA, and Elastix in low-power semiconductors. Vigyan has a PhD from the CAD group in UC Berkeley and a BTech in Computer Science from IIT Kanpur, where he graduated at the top of his class.

Jan M. Rabaey, UC Berkeley, Monday, October 24th, 2011

The Swarm at the Edge of the Cloud - the New Face of Wireless

Mobile devices such as laptops, netbooks, tablets, smart phones and game consoles have become our de facto interface to the vast amount of information delivery and processing capabilities of the cloud. The move to mobility has been enabled by the dual forces of ubiquitous wireless connectivity combined with the increasing energy efficiency offered by Moore's law. Yet, a major component of the mobile remains largely untapped: the capability to interact with the world immediately around us. A third layer of information acquisition and processing devices - commonly called the sensory swarm - is emerging, enabled by even more pervasive wireless networking and the introduction of novel ultra-low power technologies. This gives rise to the true emergence of concepts such as cyber-physical and bio-cyber systems, immersive computing, and augmented reality. The functionality of the swarm arises from connections of devices, leading to a convergence between Moore's and Metcalfe's laws, in which scaling refers not any longer to the number of transistors per chip, but rather to the number of interconnected devices. Enabling this fascinating paradigm - which represents true wireless ubiquity - still requires major breakthroughs on a number of fronts. Providing the always-connected abstraction and the reliability needed for many of the intended applications requires a careful balancing of resources that are in high demand: spectrum and energy. The presentation will analyze those challenges, and propose some disruptive solutions that engage the complete stack - from circuit to system. Addressing these concerns is one of the main focus domains of the new EECS Swarm Lab, to be located on the 4th floor of Cory, and to be officially opened on December 6.

Bio: Jan Rabaey received his Ph.D degree in applied sciences from the Katholieke Universiteit Leuven, Belgium. After being connected to UC Berkeley as a Visiting Research Engineer, he was a research manager at IMEC, Belgium. In 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley, where he now holds the Donald O. Pederson Distinguished Professorship. He is currently the scientific co-director of the Berkeley Wireless Research Center (BWRC), as well as the director of the FCRP Multiscale Systems Research Center (MuSyC). He is the recipient of a wide range of awards, amongst which are IEEE Fellow, the 2008 IEEE CAS Society Mac Van Valkenburg Award, and the 2009 European Design Automation Association (EDAA) Lifetime Achievement award. In 2010, he was awarded the prestigious Semiconductor Industry Association (SIA) University Researcher Award. His research interests include the conception and implementation of next-generation integrated wireless systems.

Jan Reineke, UC Berkeley, Monday, October 31st, 2011

Architecture-Parametric Timing Analysis

Interaction of embedded systems with their physical environment often imposes timing constraints on the embedded system's software tasks. A key step in verifying that these constraints are met is to perform worst-case execution time (WCET) analysis of the software tasks. WCET analyses rely on detailed timing models of the execution platform. The development of timing models of modern execution platforms is an extremely time-consuming and error-prone process that furthermore has to be repeated for every new execution platform. We propose to reverse this process: 1. Start by developing a timing model that enables precise and efficient WCET analysis, which can be developed once and for all. 2. Then develop different execution platforms conforming to this model. To allow for a wide range of efficient execution platforms, such a timing model can be parameterized in different architectural aspects, as for instance the sizes of different levels of the memory hierarchy and their respective latencies. In this talk, I will present a class of such parameterized timing models and a precise parametric WCET analysis technique that can be applied to this class of models.

Bio: Jan Reineke received a Bachelor's degree from the University of Oldenburg in 2003 and a Master's from Saarland University in 2005, both in Computer Science. In 2008, he defended his Ph.D. thesis on "Caches in WCET Analysis" at Saarland University. Since 2009, he has been a postdoctoral scholar at the University of California, Berkeley in the group of Edward A. Lee. His research interests include timing predictability with a focus on the memory hierarchy, WCET analysis, and static analysis by abstract interpretation, in particular cache and shape analysis.

Arkadeb Ghosal, National Instruments, Monday, November 7th, 2011

From Streaming Models to Hardware Implementations

We present a graphical programming environment, DSP Designer, for hardware design and motivate key challenges for efficient synthesis and implementation. DSP Designer aims to implement applications specified in streaming models of computation, such as Static and Cyclo-Static Dataflow, on hardware targets, such as FPGAs. Prior studies have shown the effectiveness of these models for specifying multi-rate streaming applications. However, the focus of these works has primarily been on implementations for processor targets. Hardware targets bring forth new challenges related to actor definition, IP integration, and synthesis optimizations. DSP Designer specializes common dataflow models to make them suitable for hardware targets. The framework extends dataflow actor definitions to facilitate component integration and interface synthesis in hardware. The back end supports analysis methods for resource allocation, memory optimization, and scheduler generation. The front end is an interactive graphical interface to enable application design in an intuitive manner. The objective is to deliver a rigorous design and exploration framework that empowers application domain experts to become hardware designers. In this talk, we highlight key concepts underlying DSP Designer, demonstrate preliminary capabilities for exploration and implementation using practical applications, and discuss open challenges of interest to the research community. We also summarize future directions to support heterogeneous multi-target platforms, enable more expressive models of computation that capture control along with dataflow, and include formal timing specifications.

John Eidson, UC Berkeley, Monday, November 14th, 2011

Clock Synchronization, IEEE 1588 and Recent Applications in Cyber-Physical Systems

This talk will cover the basics of network clock synchronization and how synchronized clocks are currently being applied in many areas of importance in industry and our everyday lives. Clock synchronization will be discussed in the context of IEEE 1588 and will highlight the sources of synchronization error, how these errors are being overcome and the rather remarkable results of recent field trials. The application of synchronized clocks in the field of telecommunications will be covered in some detail. Application examples from the power, industrial automation, and data acquisition industries will also be covered.

Bio: John C. Eidson received his BS and MS degrees from Michigan State University and his PhD. Degree from Stanford University all in electrical engineering. He retired in 2009 after a career in the central research laboratories of Varian Associates, Hewlett-Packard and most recently, Agilent Technologies. He is the chairperson of the IEEE 1588 standards committee. He is a life fellow of the IEEE, the recipient of the 2007 Technical Award of the IEEE I&M Society, and a co-recipient of the 2007 Agilent Laboratories Barney Oliver Award for Innovation. He is currently a visiting scholar in the PTIDES group at the University of California at Berkeley and is interested in the application of synchronized clocks to cyber-physical systems.

Timothy Bretl, University of Illinois, Monday, November 28th, 2011

Mechanics and Manipulation of Elastic Kinematic Chains

Consider a flexible wire of fixed length that is held at each end by a robot arm. The curve traced by this wire can be described as the solution to an optimal control problem, with boundary conditions that vary with the position and orientation of each robot. The set of all solutions to this problem is the configuration space of the wire under quasi-static manipulation. I will show that this configuration space is a smooth manifold of finite dimension that can be parameterized by a single chart. Working in this chart --- rather than in the space of boundary conditions --- makes the problem of manipulation planning very easy to solve. I will discuss the reasons why and will consider the application of similar ideas in other contexts, for example inference of human intent based on control-theoretic models of motor function.

Bio: Timothy Bretl received his B.S. in Engineering and B.A. in Mathematics from Swarthmore College in 1999, and his M.S. in 2000 and Ph.D. in 2005 both in Aeronautics and Astronautics from Stanford University. Subsequently, he was a Postdoctoral Fellow in the Department of Computer Science, also at Stanford University. Since 2006, he has been with the University of Illinois at Urbana-Champaign, where he is an Assistant Professor of Aerospace Engineering and a Research Assistant Professor in the Coordinated Science Laboratory. His current interests are at the intersection of robotics and neuroscience.

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