Fall 1998 CAD Seminar Schedule

  • Click on the speaker's name for a brief biography and contact information
  • Click on the title for a abstract of the talk. If we have electronic copies of transparencies or relevant papers, they can be found here, along with the abstract.
  • Please send comments and suggestions to the CAD seminar organizers.

    Month Date Day Time Venue Speaker Title
    August 19 Wed 5:00 pm Hughes Room G. Berry Implementing Synchronous Behaviors On CFSM Networks
    26 Wed 5:00 pm Hogan Room K. Shepard Static Noise Analysis for Advanced Digital VLSI Design and Cutting-Edge Silicon Technologies
    28 Fri 2:00 pm Hughes Room W. Hunt Jr. Processor Verification with Precise Exceptions and Speculative Execution
    September 2 Wed 5:00 pm Hogan Room J. Ebergen Circuits Without Clocks: What Makes Them Tick?
    9 Wed 5:00 pm Hogan Room B. Lin Software Synthesis and Co-Design based on an Asynchronous Concurrency Model
    16 Wed 5:00 pm Hogan Room S. Kang CAD for Electrothermal Reliability of Deep Submicron VLSI
    23 Wed 5:00 pm Hogan Room M. Papaefthymiou Retiming and Clock Skew Scheduling for High-Performance VLSI Design
    30 Wed 5:00 pm Hogan Room W. Roesner IBM's Cycle-Simulation-Based Verification Methodology
    October 9 Fri 2:00 pm Hughes Room J.S. Moore Proving Theorems about Commercial Microprocessors: Recent Results with ACL2
    14 Wed 5:00 pm Hogan Room A. Kahng CAD Research Productivity and Impact: Gap Analyses and Illustrations
    21 Wed 5:00 pm Hogan Room H. Saidi Automated deductive verification of reactive systems
    28 Wed 5:00 pm Hogan Room J. Grodstein Design of a Next-generation Alpha Microprocessor
    November 2 Mon 2:30 pm Hogan Room P. Godefroid "Model-Checking" Software with VeriSoft
    3 Tues 5:00 pm Hogan Room E.M. Clarke Symbolic Model Checking without BDDs
    4 Wed - - - No Seminar (FMCAD)
    6 Fri 11:00 am 373 Soda C. Visweswariah Gradient-Based Optimization of Custom Circuits
    6 Fri 3:30 pm Hogan Room M.D.F. Wong Analytical Approach To Interconnect Optimization
    11 Wed - - - No Seminar (ICCAD)
    12 Thur 2:00 pm Hughes Room N. Jha Regular-expression Based High-level Testability Analysis and Optimization
    12 Thur 5:00 pm Hogan Room E. Rudnick Genetic Algorithms for Sequential Circuit Test Generation
    13 Fri 3:30 pm Hogan Room J. Roychowdhury Multiple Time Scales for Simulation and Macromodelling of "Hard" Circuits
    16 Mon 2:30 pm Hogan Room H. Comon Constraints and Automata
    25 Wed 5:00 pm Hogan Room M. Sriram Convergence in Multistage Design Flows
    December 2 Wed 5:00 pm Hogan Room L. Lamport Verifying Cache Coherence with TLA

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